Complementary metal-oxide-semiconductor (“CMOS”) is a technology often used in fabricating integrated circuits used in microprocessors, microcontrollers, and other digital logic circuits. CMOS devices often include complementary and symmetrical pairs of field effect transistors (“FET”), namely n-type and p-type metal-oxide semiconductor field effect transistors (“MOSFET”), to form the logical gates and digital circuits.
In use, two n-type semiconductor regions (otherwise referenced as a source and a drain) are electrically-coupled by a gate. In some devices, a narrow channel, called a FIN structure, is located between the source and the drain and with a dielectric material separating the FIN structure from the gate.
Instrumental to the function of CMOS devices is electron mobility, or how quickly electrons move through a material when drawn by an electric field. For example, increased electron mobility along a FIN structure could drastically decrease energy consumption of the device without decreasing its speed. Devices using Group III-V compounds (such as InAs and InSb) and/or germanium in FIN structures and other components of the device have shown great promise in providing the desired increase in electron mobility.
However, integration of Group III-V compounds and/or germanium into conventional CMOS devices cannot be accomplished using conventional fabrication methods. A lattice-mismatch is created during conventional deposition of Group III-V compounds and/or germanium onto silicon and/or dielectric materials (such as silicon dioxide). The lattice-mismatches create dislocations, which are crystallographic defects formed during growth of a crystal structure and ultimately affect the properties of the crystal, including electron mobility. In other words, heteroepitaxial growth of a crystal adjacent a dielectric material creates a tension on the surface of the crystal in at least one lattice plane. The presence of one dislocation in one plane may be propagated to adjacent lattice planes, perpetuating the dislocation and further decreasing electron mobility. One known, conventional approach to reducing the further distortion of adjacent lattice planes is Aspect Ratio Trapping (“ART”). The ART deposition procedure is a repeated, two-step deposition-crystallization procedure configured to trap dislocations at the laterally-extending confining sidewalls of a feature. So-called buffer layers may be used to reduce the lattice mismatch between growth cycles.
However, the number of dislocations remains an issue in CMOS fabrication. There is thus a need for methods of heteroepitaxial growth of Group III-V compounds and/or germanium on dielectric materials while increasing the structural fortitude of resultant structures, such as the FIN structure.